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3rd HiPEAC
Workshop on Design for Reliability
Sunday, January 23rd, 2010
Program Schedule
11:00 - 11:10 Opening Remarks
11:10 - 12:30 Keynote Address
Session Chair: Olivier Temam, INRIA, France
Verification-Aware Architecture and
Fractal Coherence
Dan Sorin
Department of Electrical and Computer Engineering
Duke University
Abstract
When we think about designing reliable processors, we usually think
first of fault tolerance. However, another, perhaps larger challenge
in providing reliability is verifying that the processor's design is
correct. A processor is an incredibly complicated system, and
verifying that it behaves correctly -- or even specifying what it
means for it to behave correctly -- is a daunting task that consumes
a vast amount of time, engineers, and money. In this talk, I will
discuss the challenges involved in verification and propose that
architects should consider verification as a first-class design
constraint. I will then present a concrete example of
verification-aware architecture, called Fractal Coherence. Fractal
Coherence is a cache coherence protocol that we architected
specifically to be scalably verifiable.
About the Speaker
Dan Sorin is an associate professor of Electrical and Computer
Engineering at Duke University. He received his PhD from the
University of Wisconsin in 2002 and his BSE from Duke University in
1996. His research interests are in computer architecture, with
focuses on fault tolerance, verification, and memory system design.
He spent June-December 2010 on a sabbatical in a validation team at
Intel Corporation in Hillsboro, OR.
12:30 - 14:00 Lunch
14:00 - 15:35 Session I - High Level and
Architectural Reliability Mechanisms
Session Chair: Sami Yehia, THALES, France
P1. Correction of Soft Errors in
Control and Data Flow Program Segments
Ronaldo R. Ferreira, José
R. F. Azambuja, Álvaro F. Moreira
and Luigi Carro
Instituto de Informática, Universidade
Federal do Rio Grande do Sul, Porto Alegre, Brazil
P2. Concurrent and Comparative Fault
Simulation with SystemC
Waiyun Lu and Martin Radetzki
ITI Stuttgart University, Stuttgart,
Germany
P3. DanceOS: Towards Dependability
Aspects in Configurable Embedded Operating Systems*
Horst Schirmeier1, Rüdiger
Kapitza2, Daniel Lohmann2 and Olaf Spinczyk1
1Technische
Universität Dortmund, Germany
2Friedrich-Alexander-Universität
Erlangen-Nurnberg, Germany
P4. Reliable Network-Centric System
Architecture*
Gunter Schoof 1, Sergio
Montenegro2 and Vladimir Petrovic1
1IHP
GmbH, Frankfurt (Oder), Germany
2Julios-Maximilians-Universität
Wüzburg, Germany
P5. Reliability Service for
Service-Oriented Architectures*
Arkadiusz Danilecki, Mateusz Holenko,
Anna Kobusińska, Michaɫ Szychowiak, and
Piotr Zierhoffer
Institute of Computing Science, Poznań
University of Technology, Poland
15:35 - 16:00 Coffee Break
16:00 - 17:35 Application-Specific and Low-Level
Design Practices
Session Chair: Emre Ozer, ARM, UK
P6.
Robust and Low-Power
Accelerators based on Spiking Neurons for Signal Processing
Applications
Rodolphe Héliot1,2, Antoine Joubert1 and
Olivier Temam2
1CEA-LETI,
Minatec, France
2INRIA,
Saclay, Ile-De-France, France
P7. NBTI-Aware Nanoscaled Circuit
Delay Assessment and Mitigation
Seyab Khan and Said Hamdioui
Delft University of Technology,
Netherlands
P8. Statistical Modeling of
Logic Gates Based on Probabilistic Transfer Characteristics*
Thomas Coenen, Jochen Schleifer, Ahmed
Elkammar, Tobias G. Noll
RWTH Aachen University, Germany
P9. On Correcting Cluster
Errors in Nanoelectronic Circuits*
Nor Zaidi Haron and Said Hamdioui
Delft University of Technology,
Netherlands
17:35 - 18:00 Discussion and Concluding Remarks
* denotes a short paper
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